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fedl63193-04 1 semiconductor this version: sep. 2001 previous version: mar. 2000 ml63193 4-bit microcontroller with built-in 1024-dot matrix lcd driver and melody circuit. 1/37 general description the ml63193 is cmos 4 - bit microcontroller with built-in 1024-dot matrix lcd drivers (64 seg. 16 com.), and operates at 0.9 v (min). the ml63193 is suitable for applications as games, toys, watches, remote controller, etc. which are provided with a lcd display. the ml63193 is an m6318x series mask rom-version product of olms-63k family, which employs oki?s original cpu core nx-4/250. features extensive instruction set 408 instructions: transfer, rotate, increment/decrement, arithmetic operations, compare, logic operations, mask operations, bit operations, rom table reference, stack operations, flag operations, jump, conditional branch, call/return, control wide variety of addressing modes indirect addressing mode for 4 types of data memory with current bank register, extra bank register, hl register and xy register data memory bank internal direct addressing mode processing speed 2 clocks per machine cycle, with most instructions executed in 1 machine cycle minimum instruction execution time : 61 s (@ 32.768 khz system clock) : 1 s (@ 2 mhz system clock) clock generation circuit low-speed clock : crystal oscillation or rc oscillation selected with mask option (30 khz to 80 khz) high-speed clock : ceramic oscillation or rc oscillation selected with software (2 mhz max) program memory space 64 k words basic instruction length is 16 bits/1word. data memory space 2048 nibbles stack level call stack level : 16 levels register stack level : 16 levels
fedl63193-04 1 semiconductor ml63193 2/37 i/o ports input ports: selectable as input pull-up resistor/input pull-down resistor/high impedance input. i/o ports: selectable as input pull-up resistor/input pull-down resistor/high impedance input. selectable as p-channel open drain output/n-channel open drain output/high-impedance output/ cmos output. can be interfaced with external peripherals that use a different power supply than this device uses.v ddi is the power supply pin for ports. number of ports: input port : 1 port 4 bits input-output port : 5 ports 4 bits melody output melody frequency : 529 hz to 2979 hz tone length : 63 varieties tempo : 15 varieties melody data : stored in program memory buzzer driver signal output : 4 khz lcd driver number of segments : 1024 max. (64 seg. 16 com.) duty : selectable as 1/1 to 1/16 duty bias : selectable as 1/4 or 1/5 bias (regulator built-in) frame frequency : ex. 64 hz (at 1/16 duty), 128 hz (at 1/8 duty), 256 hz (at 1/4 duty), 512 hz (at 1/2 duty), 1024 hz (at 1/1 duty) contrast : 16 levels adjustable display modes : selectable as all-on mode/all-off mode/power down mode/ normal display mode multiplier/divider circuit multiplier : (8 bits) (8 bits) product (16 bits) divider : (16 bits) / (8 bits) quotient (16 bits), remainder (8 bits) system reset function system reset through reset pin (selectable as built-in 2 khz reset-sampling circuit by mask option) system reset by power-on detection (when not using 2 khz reset-sampling circuit) system reset by low-speed oscillation halt battery check low-voltage supply check the value of the judgment voltage is selected by the software (by setting the ld1 and ld0 bits of bldcon). ld1 ld0 judgment voltage (v) remarks 0 0 1.05 0.10 ta = 25 c 0 1 1.20 0.10 ta = 25 c 1 0 1.80 0.10 ta = 25 c 1 1 2.40 0.10 ta = 25 c
fedl63193-04 1 semiconductor ml63193 3/37 timers and counter 8-bit timer : 4 selectable as auto-reload mode/capture mode/ clock frequency measurement mode watchdog timer : 1 100 hz timer : 1 measurable in steps of 1/100 sec. 15-bit time-base counter : 1 1, 2, 4, 8, 16, 32, 64, and 128 hz signals can be read serial port mode : selectable as uart mode, synchronous mode uart communication speed : 1200 bps, 2400 bps, 4800 bps, 9600 bps clock frequency in synchronous mode : internal clock mode (32.768 khz), external clock frequency data length : 5 to 8 bits shift register shift clock : 1 or 1/2 system clock, timer 1 overflow, external clock data length : 8 bits interrupt factors external interrupt : 4 internal interrupt : 14 (watchdog timer interrupt is a nonmaskable interrupt) operating temperature : ?20 to +70 c power supply backup backup circuit (voltage multiplier) enables operation at 0.9 v minimum. power supply voltage when backup used : 0.9 v to 2.7 v (operating frequency: 30 k to 80 khz) 1.2 v to 2.7 v (operating frequency: 300 k to 500 khz) 1.5 v to 2.7 v (operating frequency: 200 k to 1 mhz) when backup not used : 1.8 v to 5.5 v (operating frequency: 200 k to 2 mhz) package: chip (128 pads) : (product name: ml63193-xxxwa) 144-pin plastic lqfp (lqfp144-p-2020-0.50-k) : (product name: ML63193-XXXTC) xxx indicates a code number.
fedl63193-04 1 semiconductor ml63193 4/37 mask option in the ml63193 uses the mask option to specify the following functions: ? low-speeed clock oscillation circuit specify the crystal oscillation circuit or the rc oscillation circuit for the low-speed clock oscillation circuit. ? reset signal sampling specify whether or not the reset signal will be sampled at 2 khz. when specifying ?will carry out 2 khz sampling,? hold the reset pin at a ?h? level for 1 ms or more. to use the mask option, assign mask option data in the application program in accordance with the formats below. the mask option area is an application program execution disabled area. mask option data assignment format function mask option area bit data option to be selected 0 crystal oscillation circuit low-speed clock oscillation circuit (crystal oscillation circuit/rc oscillation circuit) bit 0 1 rc oscillation circuit 0 will carry out 2 khz sampling reset signal sampling (will/will not carry out 2 khz sampling) 0ffe0h bit 1 1 will not carry out 2 khz sampling
fedl63193-04 1 semiconductor ml63193 5/37 block diagram asterisks (*) indicate the secondary function of each port. signal names enclosed by chain lines ( ) indicate interface signals of the v ddi power supply system. cpu core nx-4/250 timing con- trol cbr ebr h l x y ra mie a instruction decoder ir bus con- trol rom 64kw sp rsp c g z stack cal.s:16-level reg.s:16-level pc alu ram 2048n int193 tbc rst tst xt0 xt1 osc0 osc1 osc reset tm0cap/tm1cap* timer 8bit (4ch) tm0ovf/tm1ovf* t02ck* t13ck* sio rxc* txc* melody md v ddh back up v dd int 4 rxd* lcd & dspr com1 - 16 int 4 tst2 data bus seg0 - 63 bld wdt int 1 tst1 cb1 cb2 mdb 100hztc int 1 v dd1 bias v dd2 v dd3 v dd4 v dd5 c1 c2 v ddl v ddi v ss input port int 1 p0.0 - p0.3 i/o port p9.0 - p9.3 pa.0 - pa.3 pb.0 - pb.3 pc.0 - pc.3 int 3 int 1 int 2 muldiv txd* sft sclk* sin* sout* int 1 pe.0 - pe.3
fedl63193-04 1 semiconductor ml63193 6/37 pin configuration (top view) 144-pin plastic lqfp (tc: lqfp144-p-2020-0.50-k) note: pins marked as (nc) are no-connection pins which are left open. 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 102 101 100 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 37 38 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 65 66 67 68 69 70 71 72 105 104 103 108 107 106 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 pc.3 pc.2 pc.1 pc.0 pe.3 pe.2 pe.1 pe.0 v ddi mdb md tst2 tst1 xt0 xt1 reset osc0 osc1 v ddl v dd cb2 cb1 v ddh c2 c1 v dd5 v dd4 v dd3 v dd2 v dd1 v ss (nc) seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg59 seg60 seg61 seg62 seg63 com9 com10 com11 com12 com13 com14 com15 com16 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg39 seg38 pb.3 pa.0 pa.1 pa.2 pa.3 p9.0 p9.1 p9.2 p9.3 p0.0 p0.1 p0.2 p0.3 v ss com1 com2 com3 com4 com5 com6 com7 com8 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 pb.2 pb.1 pb.0 (nc) seg40 (nc) (nc) (nc) (nc) (nc) (nc) (nc) (nc) (nc) (nc) (nc) (nc) (nc) (nc)
fedl63193-04 1 semiconductor ml63193 7/37 pad configuration pad layout chip size : 5.72 mm 5.72 mm chip thickness : 350 m (280 m: available as required) coordinate origin : center of chip pad hole size : 100 m 100 m pad size : 110 m 110 m minimum pad pitch : 140 m note: the chip substrate voltage is v ss . seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg59 seg60 seg61 seg62 seg63 com9 com10 com11 com12 com13 com14 com15 com16 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 pb.3 pa.0 pa.1 pa.2 pa.3 p9.0 p9.1 p9.2 p9.3 p0.0 p0.1 p0.2 p0.3 v ss com1 com2 com3 com4 com5 com6 com7 com8 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 pb.2 98 pb.1 97 pb.0 96 ml63193 95 pc.3 pc.2 94 pc.1 93 92 pc.0 91 pe.3 90 pe.2 89 pe.1 88 pe.0 87 v ddi 86 mdb 85 md 84 tst2 83 tst1 82 x t0 81 x t1 80 reset 79 osc0 78 osc1 77 v ddl 76 v dd 75 cb2 74 cb1 73 v ddh 72 c2 71 c1 70 v dd5 69 v dd4 68 v dd3 67 v dd2 66 v dd1 65 v ss seg8 1 seg9 2 seg10 3 seg11 4 seg12 5 seg13 6 seg14 7 seg15 8 seg16 9 seg17 10 seg18 11 seg19 12 seg20 13 seg21 14 seg22 15 seg23 16 seg24 17 seg25 18 seg26 19 seg27 20 seg28 21 seg29 22 seg30 23 seg31 24 seg32 25 seg33 26 seg34 27 seg35 28 seg36 29 seg37 30 seg38 31 seg39 32 y x (0,0)
fedl63193-04 1 semiconductor ml63193 8/37 pad coordinates center of chip: x = 0, y = 0 pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) 1 seg8 ?2204 ?2714 44 seg51 2714 ?604 2 seg9 ?2063 ?2714 45 seg52 2714 ?464 3 seg10 ?1923 ?2714 46 seg53 2714 ?323 4 seg11 ?1783 ?2714 47 seg54 2714 ?183 5 seg12 ?1642 ?2714 48 seg55 2714 ?43 6 seg13 ?1502 ?2714 49 seg56 2714 98 7 seg14 ?1361 ?2714 50 seg57 2714 238 8 seg15 ?1221 ?2714 51 seg58 2714 379 9 seg16 ?1081 ?2714 52 seg59 2714 519 10 seg17 ?940 ?2714 53 seg60 2714 659 11 seg18 ?800 ?2714 54 seg61 2714 800 12 seg19 ?659 ?2714 55 seg62 2714 940 13 seg20 ?519 ?2714 56 seg63 2714 1081 14 seg21 ?379 ?2714 57 com9 2714 1221 15 seg22 ?238 ?2714 58 com10 2714 1361 16 seg23 ?98 ?2714 59 com11 2714 1502 17 seg24 43 ?2714 60 com12 2714 1642 18 seg25 183 ?2714 61 com13 2714 1783 19 seg26 323 ?2714 62 com14 2714 1923 20 seg27 464 ?2714 63 com15 2714 2063 21 seg28 604 ?2714 64 com16 2714 2204 22 seg29 745 ?2714 65 v ss 2152 2714 23 seg30 885 ?2714 66 v dd1 2011 2714 24 seg31 1025 ?2714 67 v dd2 1871 2714 25 seg32 1166 ?2714 68 v dd3 1730 2714 26 seg33 1306 ?2714 69 v dd4 1590 2714 27 seg34 1447 ?2714 70 v dd5 1450 2714 28 seg35 1587 ?2714 71 c1 1309 2714 29 seg36 1727 ?2714 72 c2 1169 2714 30 seg37 1868 ?2714 73 v ddh 1028 2714 31 seg38 2008 ?2714 74 cb1 888 2714 32 seg39 2149 ?2714 75 cb2 748 2714 33 seg40 2714 ?2149 76 v dd 607 2714 34 seg41 2714 ?2008 77 v ddl 467 2714 35 seg42 2714 ?1868 78 osc1 326 2714 36 seg43 2714 ?1727 79 osc0 186 2714 37 seg44 2714 ?1587 80 reset 46 2714 38 seg45 2714 ?1447 81 xt1 ?95 2714 39 seg46 2714 ?1306 82 xt0 ?235 2714 40 seg47 2714 ?1166 83 tst1 ?376 2714 41 seg48 2714 ?1025 84 tst2 ?516 2714 42 seg49 2714 ?885 85 md ?656 2714 43 seg50 2714 ?745 86 mdb ?797 2714
fedl63193-04 1 semiconductor ml63193 9/37 center of chip: x = 0, y = 0 pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) 87 v ddi ?937 2714 108 p0.0 ?2714 562 88 pe.0 ?1078 2714 109 p0.1 ?2714 421 89 pe.1 ?1218 2714 110 p0.2 ?2714 281 90 pe.2 ?1358 2714 111 p0.3 ?2714 140 91 pe.3 ?1499 2714 112 v ss ?2714 0 92 pc.0 ?1639 2714 113 com1 ?2714 ?140 93 pc.1 ?1780 2714 114 com2 ?2714 ?281 94 pc.2 ?1920 2714 115 com3 ?2714 ?421 95 pc.3 ?2060 2714 116 com4 ?2714 ?562 96 pb.0 ?2714 2246 117 com5 ?2714 ?702 97 pb.1 ?2714 2106 118 com6 ?2714 ?842 98 pb.2 ?2714 1966 119 com7 ?2714 ?983 99 pb.3 ?2714 1825 120 com8 ?2714 ?1123 100 pa.0 ?2714 1685 121 seg0 ?2714 ?1264 101 pa.1 ?2714 1544 122 seg1 ?2714 ?1404 102 pa.2 ?2714 1404 123 seg2 ?2714 ?1544 103 pa.3 ?2714 1264 124 seg3 ?2714 ?1685 104 p9.0 ?2714 1123 125 seg4 ?2714 ?1825 105 p9.1 ?2714 983 126 seg5 ?2714 ?1966 106 p9.2 ?2714 842 127 seg6 ?2714 ?2106 107 p9.3 ?2714 702 128 seg7 ?2714 ?2246
fedl63193-04 1 semiconductor ml63193 10/37 pin descriptions the basic functions of each pin of the ml63193 are described in table 1. a symbol with a slash ?/? denotes a pin that has a secondary function. refer to table 2 for secondary functions. for type, ??? denotes a power supply pin, ?i? an input pin, ?o? an output pin, and ?i/o? an input-output pin. table 1 pin descriptions (basic functions) function symbol pin no. pad no. type description v dd 50 76 ? positive power supply pin v ss 39,91 65,112 ? negative power supply pin v dd1 40 66 v dd2 41 67 v dd3 42 68 v dd4 43 69 v dd5 44 70 ? power supply pins for lcd bias (internally generated): capacitors (0.1 f) should be connected between these pins and v ss . c1 45 71 c2 46 72 ? capacitor connection pins for lcd bias generation: a capacitor (0.1 f) should be connected between c1 and c2. v ddi 61 87 ? positive power supply pin for external interface (power supply for input, and input-output ports) v ddl 51 77 ? positive power supply pin for internal logic (internally generated): a capacitor (0.1 f) should be connected between this pin and v ss . v ddh 47 73 ? voltage multiplier pin for power supply backup (internally generated): a capacitor (1.0 f) should be connected between this pin and v ss . cb1 48 74 power supply cb2 49 75 ? pins to connect a capacitor for voltage multiplier. a capacitor (1.0 f) should be connected between cb1 and cb2. xt0 56 82 i xt1 55 81 o low-speed clock oscillation pins: an option for using crystal oscillation or rc oscillation is chosen by the mask option. if the crystal oscillation is chosen, a crystal should be connected between xt0 and xt1, and capacitor (c g ) should be connected between xt0 and v ss . if the rc oscillation is chosen, external oscillation resistor (r osl ) should be connected between xt0 and xt1. osc0 53 79 i oscillation osc1 52 78 o high-speed clock oscillation pins: a ceramic resonator and capacitors (c l0 , c l1 ) or external oscillation resistor (r osh ) should be connected to these pins.
fedl63193-04 1 semiconductor ml63193 11/37 table 1 pin descriptions (basic functions) (continued) function symbol pin no. pad no. type description tst1 57 83 i test tst2 58 84 i input pins for testing. a pull-down resistor is internally connected to these pins. the user cannot use these pins. reset reset 54 80 i system reset input pin. setting this pin to ?h? level puts this device into a reset state. then, setting this pin to ? l? level starts executing an instruction from address 0000h. an option for using reset sampling circuit or not using is chosen by the mask option. when using reset sampling circuit, the system reset mode is entered by holding the reset pin at a ? h? level for 1ms or more. a pull-down resistor is internally connected to this pin. md 59 85 o melody output pin (non-inverted output) melody mdb 60 86 o melody output pin (inverted output)
fedl63193-04 1 semiconductor ml63193 12/37 table 1 pin descriptions (basic functions) (continued) function symbol pin no. pad no. type description p0.0/int5 87 108 p0.1/int5 88 109 p0.2/int5 89 110 p0.3/int5 90 111 i 4-bit input port: pull-up resistor input, pull-down resistor input, or high-impedance input is selectable for each bit. p9.0 83 104 p9.1 84 105 p9.2 85 106 p9.3 86 107 i/o pa.0 79 100 pa.1 80 101 pa.2 81 102 pa.3 82 103 i/o pb.0/int0/ tm0cap/ tm0ovf 75 96 pb.1/int0/ tm1cap/ tm1ovf 76 97 pb.2/int0/ t02ck 77 98 pb.3/int0/ t13ck 78 99 i/o pc.0/int1/ rxd 66 92 pc.1/int1/ txc 67 93 pc.2/int1/ rxc 68 94 pc.3/int1/ txd 69 95 i/o pe.0/sin 62 88 pe.1/sout 63 89 pe.2/sclk 64 90 port pe.3/int2 65 91 i/o 4-bit input output ports: in input mode, pull-up resister input, pull-down resister input, or high-impedance input is selectable for each bit. in output mode, p-channel open drain output, n- channel open drain output, cmos output, or high- impedance output is selectable for each bit.
fedl63193-04 1 semiconductor ml63193 13/37 table 1 pin descriptions (basic functions) (continued) function symbol pin no. pad no. type description com1 92 113 com2 93 114 com3 94 115 com4 95 116 com5 96 117 com6 97 118 com7 98 119 com8 99 120 com9 27 57 com10 28 58 com11 29 59 com12 30 60 com13 31 61 com14 32 62 com15 33 63 com16 34 64 o lcd common signal output pins seg0 100 121 seg1 101 122 seg2 102 123 seg3 103 124 seg4 104 125 seg5 105 126 seg6 106 127 seg7 107 128 seg8 111 1 seg9 112 2 seg10 113 3 seg11 114 4 seg12 115 5 seg13 116 6 seg14 117 7 seg15 118 8 lcd seg16 119 9 o lcd segment signal output pins
fedl63193-04 1 semiconductor ml63193 14/37 table 1 pin descriptions (basic functions) (continued) function symbol pin no. pad no. type description seg17 120 10 seg18 121 11 seg19 122 12 seg20 123 13 seg21 124 14 seg22 125 15 seg23 126 16 seg24 127 17 seg25 128 18 seg26 129 19 seg27 130 20 seg28 131 21 seg29 132 22 seg30 133 23 seg31 134 24 seg32 135 25 seg33 136 26 seg34 137 27 seg35 138 28 seg36 139 29 seg37 140 30 seg38 141 31 seg39 142 32 seg40 3 33 seg41 4 34 seg42 5 35 seg43 6 36 seg44 7 37 seg45 8 38 seg46 9 39 seg47 10 40 seg48 11 41 lcd seg49 12 42 o lcd segment signal output pins
fedl63193-04 1 semiconductor ml63193 15/37 table 1 pin descriptions (basic functions) (continued) function symbol pin no. pad no. type description seg50 13 43 seg51 14 44 seg52 15 45 seg53 16 46 seg54 17 47 seg55 18 48 seg56 19 49 seg57 20 50 seg58 21 51 seg59 22 52 seg60 23 53 seg61 24 54 seg62 25 55 lcd seg63 26 56 o lcd segment signal output pins
fedl63193-04 1 semiconductor ml63193 16/37 table 2 shows the secondary functions of each pin of the ml63193. table 2 pin descriptions (secondary functions) function symbol pin no. pad no. type description pb.0/int0 75 96 pb.1/int0 76 97 pb.2/int0 77 98 pb.3/int0 78 99 i external 0 interrupt input pins the change of input signal level causes an interrupt to occur. the port b interrupt enable register (pbie) enables or disables an interrupt for each bit. pc.0/int1 66 92 pc.1/int1 67 93 pc.2/int1 68 94 pc.3/int1 69 95 i external 1 interrupt input pins the change of input signal level causes an interrupt to occur. the port c interrupt enable register (pcie) enables or disables an interrupt for each bit. pe.3/int2 65 91 i external 2 interrupt input pin the change of input signal level causes an interrupt to occur. p0.0/int5 87 108 p0.1/int5 88 109 p0.2/int5 89 110 external interrupt p0.3/int5 90 111 i external 5 interrupt input pins the change of input signal level causes an interrupt to occur. the port 0 interrupt enable register (p0ie) enables or disables an interrupt for each bit. pb.0/ tm0cap 75 96 i timer 0 capture input pin capture pb.1/ tm1cap 76 97 i timer 1 capture input pin pb.0/ tm0ovf 75 96 o timer 0 overflow flag output pin pb.1/ tm1ovf 76 97 o timer 1 overflow flag output pin pb.2/t02ck 77 98 i external clock input pin for timer 0 and timer 2. timer pb.3/t13ck 78 99 i external clock input pin for timer 1 and timer 3
fedl63193-04 1 semiconductor ml63193 17/37 table 2 pin descriptions (secondary functions) (continued) function symbol pin no. pad no. type description pc.0/rxd 66 92 i serial port receive data input pin pc.1/txc 67 93 i/o sync serial port clock input-output pin transmit clock output when this device is used as a master processor. transmit clock input when this device is used as a slave processor. pc.2/rxc 68 94 i/o sync serial port clock input-output pin receive clock output when this device is used as a master processor. receive clock input when this device is used as a slave processor. serial port pc.3/txd 69 95 o serial port transmit data output pin pe.0/sin 62 88 i shift register receive data input pin pe.1/sout 63 89 o shift register transmit data output pin shift register pe.2/sclk 64 90 i/o shift register clock input-output pin. clock output when this device is used as a master processor. clock input when this device is used as a slave processor.
fedl63193-04 1 semiconductor ml63193 18/37 absolute maximum ratings (v ss = 0 v) parameter symbol condition rating unit power supply voltage 1 v dd1 ta = 25c ?0.3 to +1.6 v power supply voltage 2 v dd2 ta = 25c ?0.3 to +2.9 v power supply voltage 3 v dd3 ta = 25 c ?0.3 to +4.2 v power supply voltage 4 v dd4 ta = 25 c ?0.3 to +5.5 v power supply voltage 5 v dd5 ta = 25 c ?0.3 to +6.8 v power supply voltage 6 v dd ta = 25 c ?0.3 to +6.0 v power supply voltage 7 v ddi ta = 25 c ?0.3 to +6.0 v power supply voltage 8 v ddh ta = 25 c ?0.3 to +6.0 v input voltage 1 v in1 v dd input, ta = 25 c ?0.3 to v dd + 0.3 v input voltage 2 v in2 v ddi input, ta = 25 c ?0.3 to v ddi + 0.3 v output voltage 1 v out1 v dd1 output, ta = 25 c ?0.3 to v dd1 + 0.3 v output voltage 2 v out2 v dd2 output, ta = 25 c ?0.3 to v dd2 + 0.3 v output voltage 3 v out3 v dd3 output, ta = 25 c ?0.3 to v dd3 + 0.3 v output voltage 4 v out4 v dd4 output, ta = 25 c ?0.3 to v dd4 + 0.3 v output voltage 5 v out5 v dd5 output, ta = 25 c ?0.3 to v dd5 + 0.3 v output voltage 6 v out6 v dd output, ta = 25 c ?0.3 to v dd + 0.3 v output voltage 7 v out7 v ddi output, ta = 25 c ?0.3 to v ddi + 0.3 v output voltage 8 v out8 v ddh output, ta = 25 c ?0.3 to v ddh + 0.3 v storage temperature t stg ? ?55 to +150 c
fedl63193-04 1 semiconductor ml63193 19/37 recommended operating conditions ? when backup is used (v ss = 0 v) parameter symbol condition rating unit operating temperature t op ? ?20 to +70 c v dd ? 0.9 to 2.7 v operating voltage v ddi ? 0.9 to 5.5 v crystal oscillation frequency f xt c g = 5 to 25 pf 32.768 to 76.8 khz r osl = 1.0 m ? 36 30% r osl = 1.1 m ? 33 30% low-speed rc oscillation frequency f rosl r osl = 1.2 m ? 30 30% khz v dd = 0.9 to 1.2 v not applied v dd = 1.2 to 2.7 v 300 k to 500 k ceramic oscillation frequency f cm v dd = 1.5 to 2.7 v 200 k to 1 m hz v dd = 0.9 to 1.2 v not applied r osh = 400 k ? 200 k 30% r osh = 100 k ? 700 k 30% high-speed rc oscillation frequency f rosh v dd = 1.2 to 2.7 v r osh = 75 k ? 1 m 30% hz ? when backup is not used (v ss = 0 v) parameter symbol condition rating unit operating temperature t op ? ?20 to +70 c v dd ? 1.8 to 5.5 v operating voltage v ddi ? 1.8 to 5.5 v crystal oscillation frequency f xt c g = 5 to 25 pf 32.768 to 76.8 khz r osl = 1.0 m ? 36 30% r osl = 1.1 m ? 33 30% low-speed rc oscillation frequency f rosl r osl = 1.2 m ? 30 30% khz ceramic oscillation frequency f cm v dd = 1.8 to 5.5 v 200 k to 2 m hz r osh = 100 k ? 700 k 30% r osh = 75 k ? 1 m 30% v dd = 1.8 to 3.6 v r osh = 51 k ? 1.35 m 30% high-speed rc oscillation frequency f rosh v dd = 1.8 to 3.5 v, r osh = 30 k ? 2 m 30% hz
fedl63193-04 1 semiconductor ml63193 20/37 ? typical characteristics of low-speed rc oscillation when backup is used/backup is not used (v dd = v ddi = 1.5 v/v dd = v ddi = 3.0 v) ? typical characteristics of high-speed rc oscillation when backup is used (v dd = v ddi = 1.5 v) 1000 100 10 100 1000 10000 f rosl [ khz ] r osl [k ? ] reference data 10000 1000 100 10 100 1000 f rosh [ khz ] r osh [k ? ] reference data
fedl63193-04 1 semiconductor ml63193 21/37 ? typical characteristics of high-speed rc oscillation when backup is not used (v dd = v ddi = 3.0 v) 10000 1000 100 10 100 1000 f rosh [ khz ] r osh [k ? ] reference data
fedl63193-04 1 semiconductor ml63193 22/37 electrical characteristics dc characteristics (1) (v dd = v ddi = 0.9 to 5.5 v, v ss = 0 v, ta = ?20 to +70 c unless otherwise specified) parameter symbol condition min. typ. max. unit meas- uring circuit v dd2 voltage v dd2 1/5 bias, 1/4 bias (ta = 25 c) 1.7 1.8 1.9 v v dd2 voltage temperature deviation ? v dd2 ? ? ?4.0 ? mv/ c v dd1 voltage v dd1 1/5 bias, 1/4 bias typ.?0.1 1/2 v dd2 typ.+0.1 1/5 bias typ.?0.3 2/3 v dd2 typ.+0.3 v dd3 voltage v dd3 1/4 bias (connect v dd3 and v dd2 ) typ.?0.2 v dd2 typ.+0.2 1/5 bias typ.?0.4 2 v dd2 typ.+0.4 v dd4 voltage v dd4 1/4 bias typ.?0.3 3/2 v dd2 typ.+0.3 1/5 bias typ.?0.5 5/2 v dd2 typ.+0.5 v dd5 voltage v dd5 1/4 bias typ.?0.4 2 v dd2 typ.+0.4 high-speed clock oscillation stopped v dd = 1.5 v 2.8 ? 3.0 v ddh voltage (backup used) v ddh high-speed clock oscillation (ceramic oscillation, 1 mhz) v dd = 1.5 v 2.0 ? 2.7 high-speed clock oscillation stopped 1.0 1.5 2.0 v ddl voltage v ddl high-speed clock oscillation (ceramic oscillation, 1 mhz) v dd = 1.2 to 5.5 v 1.2 ? 5.5 v 1 note: 1. ? v dd2 ? changes in the range from 1.8 to 2.4 v according to the valve of display contrast register (dspcnt)
fedl63193-04 1 semiconductor ml63193 23/37 dc characteristics (2) (v dd = v ddi = 0.9 to 5.5 v, v ss = 0 v, ta = ?20 to +70 c unless otherwise specified) parameter symbol condition min. typ. max. unit meas- uring circuit crystal oscillation start voltage v sta oscillation start time: within 5 seconds 1.2 ? ? backup used 0.9 ? ? crystal oscillation hold voltage v hold backup not used 1.7 ? ? v crystal oscillation stop detect time t stop ? 0.1 ? 5.0 ms external rc oscillator capacitance c g ?5?25 internal rc oscillator capacitance c d ? 202530 external ceramic oscillator capacitance c l0 , c l1 csa2.00 mg (murata mfg.?make) used v dd = 3.0 v ?30? internal rc oscillator capacitance c os ?81216 pf v dd = 1.5 v 0 ? 0.4 por voltage v por1 v dd = 3.0 v 0 ? 0.7 v dd = 1.5 v 1.2 ? 1.5 non-por voltage v por2 v dd = 3.0 v 2 ? 3 ld1 = 1, ld0 = 1, ta = 25 c 2.30 2.40 2.50 ld1 = 1, ld0 = 0, ta = 25 c 1.70 1.80 1.90 ld1 = 0, ld0 = 1, ta = 25 c 1.10 1.20 1.30 bld judgment voltage v bldc ld1 = 0, ld0 = 0, ta = 25 c 0.95 1.05 1.15 v v bldc = 2.40 v (ld1 = 1, ld0 = 1) ? ?3.5 ? v bldc = 1.80 v (ld1 = 1, ld0 = 0) ? ?2.3 ? v bldc = 1.20 v (ld1 = 0, ld0 = 1) ? ?1.6 ? bld judgment voltage temperature deviation ? v bldc v bldc = 1.05 v (ld1 = 0, ld0 = 0) ? ?1.2 ? mv/ c 1 notes: 1. ? t stop ? indicates that if the crystal oscillator stops over the value of t stop , the system reset occurs. 2. ? por ? denotes power on reset. (when not using reset sampling circuit) 3. ? v por1 ? indicates that por occurs when v dd falls from v dd to v por1 and again rises up to v dd . 4. ? v por2 ? indicates that por dose not occur when v dd falls from v dd v por2 and again rises up to v dd .
fedl63193-04 1 semiconductor ml63193 24/37 dc characteristics (3) ? when backup is used (low-speed clock = crystal oscillation (32.768 khz), v dd = v ddi = 1.5 v, v ss = 0 v, display contrast register (dspcnt) = 0h, ta = ?20 to +70 c unless otherwise specified) parameter symbol condition min. typ. max. unit meas- uring circuit ta = ?20 to +50 c? 5.66.5 supply current 1 i dd1 cpu is in halt state. (high-speed clock oscillation stopped) ta = ?20 to +70 c ? 5.6 15.0 ta = ?20 to +50 c? 4.55.0 supply current 2 i dd2 cpu is in halt state. lcd is in power down mode. (high-speed clock oscillation stopped) ta = ?20 to +70 c ? 4.5 13.0 ta = ?20 to +50 c ? 23 26 supply current 3 i dd3 cpu is in operation at low-speed oscillation. (high-speed clock oscillation stopped) ta = ?20 to +70 c ? 23 30 supply current 4 i dd4 cpu is in operation at high-speed oscillation. (approx. 700 khz rc oscillation, r osh = 100 k ? ) ? 1100 1500 supply current 5 i dd5 cpu is in operation at high-speed oscillation. (1 mhz ceramic oscillation) ? 950 1200 a1
fedl63193-04 1 semiconductor ml63193 25/37 dc characteristics (4) ? when backup is not used (low-speed clock = crystal oscillation (32.768 khz), v dd = v ddi = 3.0 v, v ss = 0 v, display contrast register (dspcnt) = 0h, ta = ?20 to +70 c unless otherwise specified) parameter symbol condition min. typ. max. unit meas- uring circuit ta = ?20 to +50 c? 2.6 3.5 supply current 1 i dd1 cpu is in halt state. (high-speed clock oscillation stopped) ta = ?20 to +70 c? 2.6 7.0 ta = ?20 to +50 c? 2.0 2.8 supply current 2 i dd2 cpu is in halt state. lcd is in power down mode. (high-speed clock oscillation stopped) ta = ?20 to +70 c? 2.0 6.0 ta = ?20 to +50 c ? 12 13 supply current 3 i dd3 cpu is in operation at low-speed oscillation. (high-speed clock oscillation stopped) ta = ?20 to +70 c ? 12 16 supply current 4 i dd4 cpu is in operation at high-speed oscillation. (approx. 700 khz rc oscillation, r osh = 100 k ? ) ? 1000 1200 supply current 5 i dd5 cpu is in operation at high-speed oscillation. (2 mhz ceramic oscillation) ? 1100 1300 a1
fedl63193-04 1 semiconductor ml63193 26/37 dc characteristics (5) (v dd = v ddi = v ddh = 3.0 v, v dd1 = 1.1 v, v dd2 = 2.2 v, v dd3 = 3.3 v, v dd4 = 4.4 v, v dd5 = 5.5 v, ta = ?20 to +70 c unless otherwise specified) parameter symbol condition min. typ. max. unit meas- uring circuit v ddi = 1.5 v ?2.5 ?1.4 ?0.4 v ddi = 3.0 v ?6.0 ?3.5 ?1.0 i oh1 v oh1 = v ddi ? 0.5 v v ddi = 5.0 v ?8.5 ?5.0 ?1.5 v ddi = 1.5 v 0.4 1.4 2.5 v ddi = 3.0 v 1.0 3.0 6.0 output current 1 (p9.0 to p9.3) (pa.0 to pa.3) (pb.0 to pb.3) (pc.0 to pc.3) (pe.0 to pe.3) i ol1 v ol1 = 0.5 v v ddi = 5.0 v 1.5 3.7 8.5 v dd = 1.5 v ?4.0 ?2.0 ?0.5 v dd = 3.0 v ?11.0 ?6.0 ?2.0 i oh2 v oh2 = v dd ? 0.7 v v dd = v ddh = 5.0 v ?14.0 ?9.0 ?4.0 v dd = 1.5 v 0.5 2.0 4.0 v dd = 3.0 v 2.0 5.5 11.0 output current 2 (md, mdb) i ol2 v ol2 = 0.7 v v dd = v ddh = 5.0 v 4.0 7.0 14.0 ma i oh3 v oh3 = v dd5 ? 0.2 v (v dd5 level) ? ? ?4 i ohm3 v ohm3 = v dd4 + 0.2 v (v dd4 level) 4 ? ? i ohm3s v ohm3s = v dd4 ? 0.2 v (v dd4 level) ? ? ?4 i omh3 v omh3 = v dd3 + 0.2 v (v dd3 level) 4 ? ? i omh3s v omh3s = v dd3 ? 0.2 v (v dd3 level) ? ? ?4 i oml3 v oml3 = v dd2 + 0.2 v (v dd2 level) 4 ? ? i oml3s v oml3s = v dd2 ? 0.2 v (v dd2 level) ? ? ?4 i olm3 v olm3 = v dd1 + 0.2 v (v dd1 level) 4 ? ? i olm3s v olm3s = v dd1 ? 0.2 v (v dd1 level) ? ? ?4 output current 3 (seg0 to seg63) (com1 to com16) i ol3 v ol3 = v ss + 0.2 v (v ss level) 4 ? ? a v dd = v ddh = 3.0 v ?2.5 ?1.3 ?0.25 i oh4r v oh4r = v ddh ? 0.5 v (rc oscillation) v dd = v ddh = 5.0 v ?3.5 ?1.7 ?0.5 v dd = v ddh = 3.0 v 0.25 1.5 2.5 i ol4r v ol4r = 0.5 v (rc oscillation) v dd = v ddh = 5.0 v 0.5 1.8 3.5 ma v dd = v ddh = 3.0 v ?500 ?250 ?100 i oh4c v oh4c = v ddh ? 0.5 v (ceramic oscillation) v dd = v ddh = 5.0 v ?800 ?350 ?200 v dd = v ddh = 3.0 v 200 500 800 output current 4 (osc1) i ol4c v ol4c = 0.5 v (ceramic oscillation) v dd = v ddh = 5.0 v 400 700 1000 i ooh v oh = v ddi ??0.3 output leakage current (p2.0 to p2.3) (pa.0 to pa.3) (pb.0 to pb.3) (pc.0 to pc.3) (pe.0 to pe.3) i ool v ol = v ss ?0.3 ? ? a 2
fedl63193-04 1 semiconductor ml63193 27/37 dc characteristics (6) (v dd = v ddi = v ddh = 3.0 v, v dd1 = 1.1 v, v dd2 = 2.2 v, v dd3 = 3.3 v, v dd4 = 4.4 v, v dd5 = 5.5 v, ta = ?20 to +70 c unless otherwise specified) parameter symbol condition min. typ. max. unit meas- uring circuit v ddi = 1.5 v 2 20 45 v ddi = 3.0 v 30 120 260 i ih1 v ih1 = v ddi (when pulled down) v ddi = 5.0 v 70 350 650 v ddi = 1.5 v ?45 ?20 ?2 v ddi = 3.0 v ?260 ?120 ?30 i il1 v il1 = v ss (when pulled up) v ddi = 5.0 v ?650 ?350 ?70 i ih1z v ih1 = v ddi (in a high impedance state) 0?1 input current 1 (p0.0 to p0.3) (p9.0 to p9.3) (pa.0 to pa.3) (pb.0 to pb.3) (pc.0 to pc.3) (pe.0 to pe.3) i il1z v il1 = v ss (in a high impedance state) ?1 ? 0 v dd = v ddh = 3.0 v ?350 ?170 ?30 i il2 v il2 = v ss (when pulled up) v dd = v ddh = 5.0 v ?750 ?450 ?200 i ih2r v ih2r = v ddh (rc oscillation) 0 ? 1 i il2r v il2r = v ss (rc oscillation) ?1 ? 0 v dd = v ddh = 3.0 v 0.5 1.8 4.0 i ih2c v ih2c = v ddh (ceramic oscillation) v dd = v ddh = 5.0 v 3 6 10 v dd = v ddh = 3.0 v ?4.0 ?1.8 ?0.5 input current 2 (osc0) i il2c v il2c = v ss (ceramic oscillation) v dd = v ddh = 5.0 v ?10 ?6 ?3 v dd = 1.5 v 10 180 350 v dd = 3.0 v 150 1100 2400 a i ih3 v ih3 = v dd v dd = v ddh = 5.0 v 0.5 2.7 5.0 ma input current 3 (reset) i il3 v il3 = v ss ?1 ? 0 v dd = 1.5 v 50 750 1500 a v dd = 3.0 v 0.5 3.0 5.5 i ih4 v ih4 = v dd v dd = v ddh = 5.0 v 2.0 6.5 11.0 ma input current 4 (tst1, tst2) i il4 v il4 = v ss ?1 ? 0 a 3
fedl63193-04 1 semiconductor ml63193 28/37 dc characteristics (7) (v dd = v ddi = v ddh = 3.0 v, v dd1 = 1.1 v, v dd2 = 2.2 v, v dd3 = 3.3 v, v dd4 = 4.4 v, v dd5 = 5.5 v, ta = ?20 to +70 c unless otherwise specified) parameter symbol condition min. typ. max. unit meas- uring circuit v ddi = 1.5 v 1.2 ? 1.5 v ddi = 3.0 v 2.4 ? 3.0 v ih1 v ddi = 5.0 v 4.0 ? 5.0 v ddi = 1.5 v 0 ? 0.3 v ddi = 3.0 v 0 ? 0.6 input voltage 1 (p0.0 to p0.3) (p9.0 to p9.3) (pa.0 to pa.3) (pb.0 to pb.3) (pc.0 to pc.3) (pe.0 to pe.3) v il1 v ddi = 5.0 v 0 ? 1 v dd = v ddh = 3.0 v 2.4 ? 3.0 v ih2 v dd = v ddh = 5.0 v 4.0 ? 5.0 v dd = v ddh = 3.0 v 0 ? 0.6 input voltage 2 (osc0) v il2 v dd = v ddh = 5.0 v 0 ? 1 v dd = 1.5 v 1.35 ? 1.5 v dd = 3.0 v 2.4 ? 3.0 v ih3 v dd = 5.0 v 4.0 ? 5.0 v dd = 1.5 v 0 ? 0.15 v dd = 3.0 v 0 ? 0.6 input voltage 3 (reset), (tst1), (tst2) v il3 v dd = 5.0 v 0 ? 1 v ddi = 1.5 v 0.05 0.1 0.3 v ddi = 3.0 v 0.2 0.5 1.0 hysteresis width 1 (p0.0 to p0.3) (p9.0 to p9.3) (pa.0 to pa.3) (pb.0 to pb.3) (pc.0 to pc.3) (pe.0 to pe.3) ? v t1 v ddi = 5.0 v 0.25 1.0 1.5 v dd = 1.5 v 0.05 0.1 0.3 v dd = 3.0 v 0.2 0.5 1.0 hysteresis width 2 (reset), (tst1), (tst2) ? v t2 v dd = 5.0 v 0.25 1.0 1.5 v4 input pin capacitance (p0.0 to p0.3) (p9.0 to p9.3) (pa.0 to pa.3) (pb.0 to pb.3) (pc.0 to pc.3) (pe.0 to pe.3) c in ???5pf1
fedl63193-04 1 semiconductor ml63193 29/37 measuring circuit 1 c a , c b , c c , c d , c e , c l , c 12 :0.1 f c h , c b12 :1 f c g : 15 pf c l0 : 30 pf c l1 : 30 pf ceramic resonator : csa2.00mg (2 mhz) csb1000j (1 mhz) (murata mfg.-make) v v ca cc v dd3 v dd1 v ddi v ss xt0 xt1 *1 rc oscillator r osh ceramic oscillator c l0 cb12 cb1 cb2 osc0 osc1 a v dd v cd v dd4 c l1 ceramic resonator *1 c12 c1 c2 v cb v dd2 ce v dd5 v v ch v ddh cl v ddl v *2 *2 rc oscillator r osl crystal oscillator c g crystal 1 2 3 4 1 2 1 2 3 4 3 4
fedl63193-04 1 semiconductor ml63193 30/37 measuring circuit 2 measuring circuit 3 measuring circuit 4 v ih input *3 v il a *4 *3 input logic circuit to determine the specified measuring conditions. *4 measured at the specified output pins. v dd4 v dd3 v dd1 v ss v dd v dd2 v dd5 v ddh v ddl v ddi output v dd3 v dd2 a *5 v ddi v ss v dd v dd1 v dd4 v ddh v dd5 v ddl input output v ih *5 v il *5 measured at the specified input pins. waveform monitoring v dd3 v dd2 v ddi v dd v dd1 v dd4 v ddh v dd5 v ss v ddl input output
fedl63193-04 1 semiconductor ml63193 31/37 ac characteristics (serial interface, serial port) (1) synchronous communication (v dd = 0.9 to 5.5 v, v ddh = 1.8 to 5.5 v, v ss = 0 v, v ddi = 5.0 v, ta = ?20 to +70 c unless otherwise specified) parameter symbol condition min. typ. max. unit txc/rxc input fall time t f ???1.0 txc/rxc input rise time t r ???1.0 txc/rxc input ?l? level pulse width t cwl ?0.8?? txc/rxc input ?h? level pulse width t cwh ?0.8?? txc/rxc input cycle time t cyc ?2.0?? txc/rxc output cycle time t cyc (o) cpu is in operating at 32.768 khz ? 30.5 ? txd output delay time t ddr output load capacitance 10 pf ??0.4 rxd input setup time t ds ?0.5?? rxd input hold time t dh ?0.8?? s synchronous communication timing (?h? level = 4.0 v, ?l? level = 1.0 v) t r t f t cwh t cwl t ddr t ddr t cyc t ds t ds t dh v ddi v ss v ddi v ss v ddi v ss txc (pc.1)/ rxc (pc.2) txd (pc.3) rxd (pc.0)
fedl63193-04 1 semiconductor ml63193 32/37 (2) uart communication parameter symbol condition min. typ. max. unit transmit baud rate t brt t brt = 1/f brt t cr = 1/f osc t brt ? t cr t brt t brt + t cr receive baud rate r brt r brt = 1/f brt r brt 0.97 r brt r brt 1.03 s f brt : baud rates (1200, 2400, 4800, 9600 bps) uart communication timing (?h? level = 4.0 v, ?l? level = 1.0 v) t brt v ddi v ss txd (pc.3) r brt v ddi v ss rxd (pc.0)
fedl63193-04 1 semiconductor ml63193 33/37 ac characteristics (serial interface, shift register) (v dd = 0.9 to 5.5 v, v ddh = 1.8 to 5.5 v, v ddi = 5.0 v, v ss = 0 v, ta = ?20 to +70 c unless otherwise specified) parameter symbol condition min. typ. max. unit sclk input fall time t f ???1.0 sclk input rise time t r ???1.0 sclk input ?l? level pulse width t cwl ?0.8?? sclk input ?h? level pulse width t cwh ?0.8?? sclk input cycle time t cyc 1.8 ? ? t cyc1(o) cpu is in operating at 32.768 khz ? 30.5 ? sclk output cycle time t cyc2(o) cpu is in operating at 2 mhz v dd = v ddh = 1.8 to 3.5 v ?0.5? sout output delay time t ddr c l = 10 pf ? ? 0.4 sin input setup time t ds ?0.5?? sin input hold time t dh ?0.8?? s ac characteristics timing (?h? level = 4.0 v, ?l? level = 1.0 v) t r t f t cwh t cwl t ddr t ddr t cyc t ds t ds t dh v ddi v ss v ddi v ss v ddi v ss sclk (pe.2) sout (pe.1) sin (pe.0)
fedl63193-04 1 semiconductor ml63193 34/37 application circuits note: v ddi is the power supply pin for the input-output ports. be sure to connect the v ddi pin either to the positive power supply pin (v dd ) of this device or to the positive power supply pin of the external memory. application circuit example with power supply backup xt0 com1-16 xt1 v ddh v dd cb1 cb2 v dd5 v dd4 v dd3 v dd2 v dd1 c1 c2 reset tst1 tst2 md mdb v ss seg0-63 osc0 osc1 r osh c b12 c v c g c 12 lcd crystal 32.768 khz c h 1.5 v c e c d c c c b c a buzzer ? crystal oscillation is selected as low-speed oscillation by mask option. ? rc oscillation is selected as high-speed oscillation by software. ? ports are powered from external memory power source. ? c v is an ic power supply bypass capacitor. ? values of c a , c b , c c , c d , c e , c l , c b12 , c 12 , c h , and c g , are for reference only. v ddl c l push sw 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 1.0 f 0.1 f 1.0 f 5 to 25 pf ml63193 1.0 f v ddi v dd pe.1 pe.0 pe.3 pe.2 pc.1 pc.0 pc.3 pc.2 pb.1 pb.0 pb.3 pb.2 pa.1 pa.0 pa.3 pa.2 p9.1 p9.0 p9.3 p9.2 p0.1 p0.0 p0.3 p0.2
fedl63193-04 1 semiconductor ml63193 35/37 note: v ddi is the power supply pin for the input-output ports. be sure to connect the v ddi pin either to the positive power supply pin (v dd ) of this device or to the positive power supply pin of the external memory. application circuit example with no power supply backup xt0 com1-16 xt1 v ddh v dd v dd5 v dd4 v dd3 v dd2 v dd1 c1 c2 reset tst1 tst2 md mdb v ss seg0-63 osc0 osc1 c v c g c 12 lcd crystal 32.768 khz v dd 5.0 v c e c d c c c v c a buzzer ? crystal oscillation is selected as low-speed oscillation by mask option. ? ceramic oscillation is selected as high-speed oscillation by software. ? ports, external memory, and ic share their power supply. ? c v is an ic power supply bypass capacitor. ? values of c a , c b , c c , c d , c e , c l , c 12 , c g , c l0 , and c l1 are for reference only. c l0 30 pf c l1 30 pf ceramic resonator (example: 1 mhz) cb1 cb2 v ddl c l ml63193 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f open push sw 5 to 25 pf 0.1 f v ddi v dd pe.1 pe.0 pe.3 pe.2 pc.1 pc.0 pc.3 pc.2 pb.1 pb.0 pb.3 pb.2 pa.1 pa.0 pa.3 pa.2 p9.1 p9.0 p9.3 p9.2 p0.1 p0.0 p0.3 p0.2
fedl63193-04 1 semiconductor ml63193 36/37 package dimensions lqfp144-p-2020-0.50-k mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 1.37 typ. 5 rev. no./last revised 5/nov. 28, 1996 notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact oki?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (unit : mm)
fedl63193-04 1 semiconductor ml63193 37/37 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2001 oki electric industry co., ltd.

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